Chip Design Reinvented

The Role

We are looking for a Head of AI who will lead our AI engineering team and personally build the core systems that generate and optimize chip designs. This is a hands-on technical leadership role—you will write code, train models, and set the technical direction for AI-powered hardware design.

In this role, you will own everything AI: the RTL generation models that write Verilog, self-verification loop and optimization and domain space explorations that makes our AI get better with every cycle. You will build a world-class team while staying deeply technical. This is a founding leadership position with a path to Chief AI Officer as we scale.

What You Will Do

• Set AI Technical Vision: Define the architecture and roadmap for our AI systems. You will make the critical decisions on model architecture, training strategy, and system design that determine our technical trajectory.
• Build RTL Generation Systems: Lead development of LLMs that generate production-quality Verilog/SystemVerilog. You will personally architect the systems that transform specifications into silicon-ready designs.
• Develop optimization and design space exploration loop: Own the feedback system where verification results improve model efficacy. You will design the architecture that enables our AI to learn all the designs that are generated, fixed and optimized.
• Lead Document Understanding: Build systems that parse architecture specs, design documents, and protocol definitions into structured representations our models can use.
• Hire and Develop the Team: Build the AI engineering team to a large team over the next three years. You will recruit top talent, set technical standards, and mentor engineers.
• Partner with Chip Design: Work closely with our chip design and verification engineers to ensure AI-generated designs meet production quality standards. You will bridge the gap between AI and hardware.
• Drive Research Agenda: Identify and pursue research directions that advance our capabilities. You will keep us at the frontier of AI for hardware design.

What You Bring (Required)

• AI/ML Leadership: 8+ years of experience in ML/AI, with years of experience in leading teams. Shipped production AI systems that handle real-world complexity.
• LLM Expertise: Deep hands-on experience with large language models—dataset creation, training, fine-tuning, and deployment. Understand transformer architectures, scaling laws, and the practical challenges of production LLM systems.
• AI Agents and Code Generation: Worked on AI agents and code generation, program synthesis, or compiler systems.
• Hands-on: Experience building AI agent systems, with proficiency in Python and PyTorch.
• Team Building: Hired and developed AI engineers. You can identify exceptional talent and create an environment where they do their best work.
• Systems Thinking: Design systems that integrate models with infrastructure, data pipelines, and user workflows.

Bonus Points (Preferred)

• Previous leadership role at a top AI labs or AI-focused startup.
• Background in reinforcement learning, especially learning from feedback or verification and PPA signals.
• Experience with document understanding, RAG systems, or structured information extraction.
• MS or PhD in Computer Science, Machine Learning, or related field.

Why Join Us

We are in the midst of a massive AI infrastructure build-up requiring ways to design chips rapidly and efficiently—yet chip design methodology has not kept pace with growing complexity, and the talent pool is aging.

• Shape the future of chip design by building "tools that build the chips"
• Work at the intersection of AI, automation, and silicon design
• Your software will multiply the productivity of entire engineering organizations
• Join a team that values software best practices applied to the hardware domain

The Role

We are looking for an AI System Engineer who builds the core AI systems that generate and optimize chip designs. You will develop models that write RTL, understand power-performance-area tradeoffs, and learn from verification feedback to continuously improve.

In this role, you will work on derivative design generation—transforming existing RTL based on delta specifications—and the self-improvement loop that makes our AI get better over time. You will build AI that writes hardware, not just software. This is one of the most challenging and rewarding problems in applied AI today.

What You Will Do

• Build Code Generation Models: Develop and fine-tune LLMs that generate syntactically and functionally correct Verilog/SystemVerilog with the best power-performance-area.
• Develop Derivative Design Generation: Build systems that take existing RTL and a delta specification, and produce modified RTL that implements the requested changes while preserving correctness.
• Design Space Exploration: Build algorithms that automatically explore the design space, proposing delta specs that improve PPA (power, performance, area) while maintaining functionality.
• Optimize Inference: Ensure our models run fast enough for interactive use. You will optimize inference latency and throughput for production deployment.
• Curate Training Data: Develop pipelines to collect, clean, and curate training data from verified designs. Data quality is model quality.

What You Bring (Required)

• LLM/Transformer Expertise: Deep experience with dataset preparation and creation, large language models, transformer architectures, and their training. You understand attention mechanisms, tokenization strategies, and scaling laws.
• Code Generation Experience: Worked on code generation systems. You understand the unique challenges of generating executable code versus natural language.
• PyTorch/JAX Proficiency: Expert-level skills in PyTorch or JAX. You can implement custom model architectures and training loops.
• Distributed Training: Experience training large models across multiple GPUs/TPUs.
• Reinforcement Learning: Familiarity with RL concepts.

Bonus Points (Preferred)

• Experience at AI labs and/or AI startups.
• Background in compilers, program synthesis, or formal methods.
• Understanding of hardware design concepts (RTL, synthesis, timing, PPA).
• Experience with code LLMs.
• MS or PhD in Computer Science with ML focus.

Why Join Us

You will build AI that designs chips—one of the most complex engineering artifacts humans create. This isn't incremental improvement; it's a fundamental shift in how chips are designed.

• Shape the future of chip design by building "tools that build the chips"
• Work at the intersection of AI, automation, and silicon design
• Your software will multiply the productivity of entire engineering organizations
• Join a team that values software best practices applied to the hardware domain

The Role

We are looking for an AI Application Engineer who transforms unstructured materials—documents, code, specifications, diagrams—into structured representations that our AI system uses for chip design generation. You will build the bridge between messy real-world inputs and precise architectural specifications.

In this role, you will develop systems that can parse everything from PDF datasheets to legacy Verilog code, extracting the information our AI needs to generate and modify chip designs. Your work enables customers to use their existing documentation and collateral with our platform, dramatically reducing the barrier to AI-assisted chip design.

What You Will Do

• Build Document Understanding Systems: Develop parsers and extractors for PDFs, Word documents, wikis, and other unstructured formats. Your systems will understand technical content—not just extract text.
• Develop Code Analysis Pipelines: Build systems that analyze Verilog, SystemVerilog, and C code to extract architectural intent, interfaces, and constraints.
• Create Multi-Modal Understanding: Go beyond text. You will build systems that understand diagrams, waveforms, timing charts, and tables—the visual language of chip design.
• Build RAG Systems: Develop Retrieval Augmented Generation pipelines that provide relevant context from large document corpora to our design generation models.
• Extract Delta Specifications: Parse customer change requests and modification specs into structured formats that drive derivative design generation.
• Collaborate with Chip Designers: Work closely with chip design engineers to ensure your systems accurately capture architectural intent and design constraints.

What You Bring (Required)

• AI Agents and LLM Expertise: Deep experience with large language models and AI agents. Build applications on top of LLMs.
• Python Mastery: Expert-level Python skills and experience building production ML systems.
• Document Parsing Experience: Built systems that extract structured information from PDFs, Word documents, or other unstructured formats.
• RAG Systems: Experience building retrieval systems, working with embeddings, and integrating vector databases.
• Code Analysis: Familiarity with AST parsing, static analysis, or compiler techniques.
• Problem-Solving Mindset

Bonus Points (Preferred)

• Experience at AI labs or startup companies focused on AI.
• Experience with computer vision for diagram or waveform understanding.
• Knowledge of chip design concepts (architecture specs, interface protocols, timing diagrams).
• MS or PhD in Computer Science with NLP or ML focus.

Why Join Us

You will build AI that designs chips—one of the most complex engineering artifacts humans create. This isn't incremental improvement; it's a fundamental shift in how chips are designed.

• Shape the future of chip design by building "tools that build the chips"
• Work at the intersection of AI, automation, and silicon design
• Your software will multiply the productivity of entire engineering organizations
• Join a team that values software best practices applied to the hardware domain

The Role

We are looking for a Chip Design Engineer who works on strategic customer engagements, developing custom IP and optimizing designs for power, performance, and area. You will collaborate closely with our AI systems, providing the domain expertise that ensures AI-generated designs meet real-world requirements.

In this role, you will combine hands-on RTL design with exposure to cutting-edge AI technology. You will help shape how AI and human expertise work together in chip design. Your designs will go into production at the world's leading technology companies.

What You Will Do

• Design RTL for Customer Projects: Implement RTL for strategic customer engagements. You will write clean, synthesizable, timing-aware Verilog/SystemVerilog.
• Optimize for PPA: Analyze and optimize designs for power, performance, and area. Your optimizations will contribute to royalty-generating designs.
• Support Synthesis and Timing: Work through synthesis and timing closure. You understand what makes RTL synthesizable and how to fix timing violations.
• Improve AI-Generated Designs: Review and enhance AI-generated RTL for production quality. Your feedback will improve model accuracy.
• Develop Reference Implementations: Create high-quality reference designs that become training data for our AI models.
• Implement Protocol Blocks: Build protocol implementations (PCIe, DDR, AXI, etc.) for customer requirements.

What You Bring (Required)

• RTL Design Experience: You have 5+ years of experience designing production RTL. You write clean, readable, synthesizable Verilog/SystemVerilog.
• Micro-Architecture Understanding: You have solid understanding of pipeline design, FSMs, arbitration, and data flow. You can translate architecture specs into RTL.
• Synthesis Awareness: You have experience with synthesis tools (Design Compiler, Genus). You understand what makes RTL timing-friendly.
• Debug Skills: You can read waveforms, trace signal paths, and debug complex logic issues. You have experience with Verdi, SimVision, or similar tools.
• PPA Intuition: You understand power-performance-area tradeoffs. You can make informed design decisions based on PPA goals.
• Collaborative Mindset: You work well with verification engineers, architects, and AI engineers. You communicate clearly and give/receive feedback well.

Bonus Points (Preferred)

• Experience at leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm, Broadcom, Marvell, MediaTek).
• Protocol implementation experience (PCIe, DDR, AXI, AHB, APB, CHI).
• Physical design awareness (floor planning, clock tree, routing congestion).
• Background in accelerator, SoC, or high-performance computing design.
• Familiarity with AI/ML concepts and interest in AI-assisted design.
• MS in Electrical Engineering or Computer Science.

Why Join Us

You will be at the forefront of AI-assisted chip design—a fundamental transformation in how chips are built. Your designs will go into production at top tech companies. You'll learn cutting-edge AI while applying your chip design expertise, building skills that will define the future of the industry.

The Role

We are looking for a Chip Design and Verification Methodology Engineer who develops innovative methodologies to design and verify chip designs with a massive boost in productivity and quality. We treat verification as a design discipline in a holistic manner—not just a testing phase.

In this role, you will ensure the functional correctness of AI-generated RTL while fundamentally changing the way we design and verify chips. You will architect the verification loop that performs maximal automation, finds the "impossible" bugs, proves correctness, and lays the foundation for improving power-performance-area (PPA) rapidly. Your work is the foundation that makes AI-generated chip design usable and trustworthy.

What You Will Do

• Drive Verification Methodology and Environment: Take responsibility for the full verification lifecycle of AI-generated RTL with maximal automation. You will build the verification loop that catches bugs, generates actionable feedback, and enables AI models to improve.
• Architect Test Environments: Write clean, modular, and reusable verification environments/harnesses that can scale across customer designs. Your environments will integrate simulation, formal verification, and emulation into a unified flow.
• Build Convergence Monitoring: Develop systems that track verification progress, measure coverage, and provide guarantees about design correctness. You will define what "done" means for AI-generated designs.
• Deep-Dive Debugging: Go beyond pass/fail logs. You will build advanced tools to read, parse, and analyze waveforms, tracing signal dependencies to pinpoint the root cause of logic failures and feed actionable information back to AI models.
• Collaborate on AI Integration: Work closely with AI engineers to ensure verification feedback improves model accuracy. Your understanding of what makes RTL correct will shape how our AI learns.
• Formal Proof Generation: Develop formal proofs for critical design paths, ensuring that safety-critical properties hold under all conditions.

What You Bring (Required)

• Verilog and SystemVerilog Fluency: You have expert-level proficiency in writing Verilog and SystemVerilog. You understand the nuances of the language for both design (RTL) and verification (TB).
• SystemVerilog Assertions: You have strong experience writing SystemVerilog Assertions. You know how to write concurrent assertions to validate complex temporal protocols.
• UVM Expertise: You have deep experience with UVM methodology, including constrained-random verification, functional coverage, and scoreboards.
• Computer Architecture Fundamentals: You possess a solid understanding of Computer Architecture and Digital Design fundamentals (e.g., pipelines, FSMs, clock domain crossing, memory hierarchy, and coherence protocols).
• Waveform Analysis: You have proven ability to read and analyze simulation waveforms (using tools like Verdi, SimVision, or DVE) to resolve complex logic issues.
• Automation Mindset: You have strong Python/scripting skills and a passion for automating everything that can be automated.

Bonus Points (Preferred)

• Hands-on experience with commercial formal tools such as JasperGold or VC Formal. Experience with formal apps (Connectivity, CDC, RDC, CSR) is highly desirable.
• Deep knowledge of standard on-chip interface protocols like AXI, AHB, APB, CHI, PCIe, or CXL.
• Experience at EDA vendors (Synopsys, Cadence, Siemens) or leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm).
• Background in emulation platforms (Palladium, Veloce, ZeBu).
• Familiarity with AI/ML concepts and interest in how AI can transform chip design.
• MS or PhD in Electrical Engineering or Computer Science.

Why Join Us

You will be building the foundation of a new way to design chips. Verification is what makes AI-generated RTL trustworthy—your work enables everything else. You'll work at the intersection of traditional chip verification and cutting-edge AI, solving problems no one has solved before.